基本信息：
林智锋，副教授，福州大学立芯电子设计自动化创新研究院负责人。主要研究方向为集成电路电子设计自动化、智能EDA算法等。在EDA领域的顶级期刊TCAD、TODAES以及四大国际会议DAC、ICCAD、DATE、ASPDAC等发表论文40余篇，申请和授权国家发明专利近20项（其中专利成果转化1项）。获2025年CCF容错计算专委40周年卓越成果，2020年和2023年国际集成电路计算机辅助设计竞赛（CAD Contest@ICCAD）第二名，2024年国际集成电路物理设计竞赛（ISPD Contest）第三名。主持国家级GF项目、福建省自然科学基金以及华为、上海立芯等企业横向项目。
主要科研项目：
1．国家级GF项目，***引擎，250万，2023.12-2025.12，主持
2. 福州立芯科技有限公司，面向3DIC的布局布线与物理验证关键技术研发， 300万，2025.10-2027.12，主持
3. 华为技术有限公司，基于模糊匹配的模块复用技术，54万，2023.11-2024.12，主持
4. 上海立芯软件科技有限公司，时序驱动的VLSI混合高度单元布局研究，100万，2023.1-2024.12，主持
获奖情况：
1．2025年CCF容错计算专委40周年卓越成果
2. 2024年福建省教学成果奖一等奖
3. 2024年国际集成电路物理设计竞赛（ISPD Contest）第三名
4. 2023年集成电路EDA设计精英挑战赛全国一等奖，赛题第一
5. 2023年国际集成电路计算机辅助设计竞赛（CAD Contest@ICCAD）第二名
6. 2023年福州大学青年五四奖章
7. 2020年国际集成电路计算机辅助设计竞赛（CAD Contest@ICCAD）第二名
8. 2019年“互联网+”中国大学生创新创业大赛金奖，创意组全国第一名
主要论著：
1. Xiqiong Bai, Daiwei Zhang, Xiutao Yan, Zhifeng Lin, Kun Wang, Ziran Zhu, Jianli Chen, Zhikuang Cai, Late Breaking Results: Scalable OARSMT Generation via Predictive Topological Reduction in VLSI Routing, ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026. (CCF-A)
2. Guohao Chen, Chang Liu, Xingyu Tong, Peng Zou, Jianli Chen, Zhifeng Lin*, A Co-optimization Framework for Multi-layer Design Rule Constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), 31(4):1-28, 2026. (CCF-B)
3. Zhaoyi Wu, Haishan Huang, Jianli Chen, Zhifeng Lin∗, An Adaptive Cost-based Via and Congestion Co-optimization Framework for VLSI Global Routing, IEEE/ACM Design, Automation and Test in Europe (DATE), Verona, Italy, Apr. 20-22, 2026. (CCF-B)
4. Zhaoyi Wu, Haishan Huang, Benchao Zhu, Jianli Chen, Zhifeng Lin*, Layer-Aware Timing-Driven Global Routing for Advanced Technology Nodes, IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, May 24-27,2026. (CCF-B)
5. Chuandong Chen, Disi Lin, Qinghai Liu, Huan He, Zhifeng Lin*, Genggeng Liu, Jianli Chen, Yao-Wen Chang, A Matching Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 44(12):4765 – 4778, 2025 (CCF-A)
6. Genggeng Liu, Ren Lu, Yuhan Zhu, Zhifeng Lin, Chuandong Chen, Min Gan, Jianli Chen, Wenzhong Guo, Obstacle-Avoiding X-Architecture Bounded-Skew Tree Algorithm Under Timing Slack Constraints, IEEE Transactions on Systems, Man, and Cybernetics: Systems, 55(12):9426-9440, 2025. (中科院TOP期刊)
7. Benchao Zhu, Guohao Chen, Jiawei Li, Peng Zou, Haokai Sun, Zhifeng Lin*, Jianli Chen, Legalization Framework with Design Rule Constraints Enhanced by Monte-Carlo-Based Cell Priority Optimization, IEEE International Symposium on Circuits and Systems (ISCAS), London, May 25-28, 2025. (CCF-B)
8. Tingxuan Gong, Wenxu Ruan, Dongwei Tan, Zhendong He, Zhifeng Lin*, Jianli Chen, Multi-Bit Flip-Flop Based Timing and Power Optimization under Advanced Technology Nodes, IEEE International Symposium on Circuits and Systems (ISCAS), London, May 25-28, 2025. (CCF-B)
9. Zhijie Cai, Min Wei, Peng Zou, Xiqiong Bai, Zhifeng Lin*, Jianli Chen, Analytical Layer Assignment with Simulated Annealing Refinement, IEEE International Symposium on Circuits and Systems (ISCAS), London, May 25-28, 2025. (CCF-B)
10. Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang, Electrostatics-Based Analytical Global Placement for Timing Optimization, IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Mar. 25-27, 2024.(CCF-B)
11. Xingyu Tong, Guohao Chen, Min Wei, Zhijie Cai, Peng Zou, Zhifeng Lin*, Jianli Chen, Layout-level Hardware Trojan Prevention in the Context of Physical Design, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27–31, 2024. (CCF-B)
12. Jihai Meng, Shaohong Weng, Zhijie Cai, Yilu Chen, Zhifeng Lin*, Jianli Chen, Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion, IEEE/ACM Design Automation Conference (DAC), San Francisco, Jun. 23-27, 2024.(CCF-A)
13. Yilu Chen, Zhijie Cai, Min Wei, Zhifeng Lin*, Jianli Chen, Global and Local Attention-Based Inception U-Net for Static IR Drop Prediction, IEEE International Conference on Computer Design (ICCD), Milan, Nov. 18-20, 2024. (CCF-B)
14. Yilu Chen, Zhifeng Lin*, Xiaojian Liang, Zhijie Cai, Xiqiong Bai, and Jianli Chen, Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 71(9), pp. 4201-4205, 2024. (中科院TOP期刊)
15. Peng Zou, Guohao Chen, Zhifeng Lin, Jun Yu and Jianli Chen, Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 09-13, 2023. (CCF-A)
16. Peng Zou, Zhijie Cai, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen, Incremental 3D Global Routing Considering Cell Movement and Complex Routing Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 42(6):2016-2029, 2023. (CCF-A)
17. Zhifeng Lin, Yanyue Xie, Peng Zou, Sifei Wang, Jun Yu and Jianli Chen, An Incremental Placement Flow for Advanced FPGAs with Timing Awareness, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 40(9):3092-3103, 2022. (CCF-A)
18. Jianli Chen, Zhifeng Lin, Yanyue Xie, Wenxin Zhu and Yao-Wen Chang, Mixed-cell-height Placement with Complex Minimum-Implant-Area Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(11): 4639-4652, 2022. (CCF-A)
19. Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu and Yao-Wen Chang, Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints, IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, Feb. 01-05, 2021. (CCF-B)
20. Peng Zou, Zhifeng Lin, Chenyue Ma, Jun Yu and Jianli Chen, Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement, ACM/IEEE Design Automation Conference (DAC), San Francisco, Dec. 5-9, 2021. (CCF-A)
21. Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu and Jianli Chen, Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 19-23, 2020. (CCF-A)
22. Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, and Sy-Yen Kuo, Clock-Aware Placement for Large-Scale Heterogeneous FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(12):5042-5055, 2020. (CCF-A)
23. Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, and Yao-Wen Chang, Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 19-23, 2020. (CCF-A)
