基本信息：
林智锋，副教授，硕士生导师，主要研究方向为集成电路设计自动化、智能EDA算法等。在EDA领域的主要会议/期刊（例如：TCAD、DAC、ICCAD、DATE、ASPDAC等）发表论文三十余篇，申请和授权国家发明专利10余项。主持国家级GF项目、福建省自然科学基金以及华为、上海立芯等企业横向课题。
获奖情况：
1．2025年CCF容错计算专委40周年代表性成果
2. 2024年福建省教学成果奖一等奖
3. 2024年国际集成电路物理设计竞赛（ISPD Contest）第三名
4. 2023年集成电路EDA设计精英挑战赛全国一等奖，赛题第一
5. 2023年国际集成电路计算机辅助设计竞赛（CAD Contest@ICCAD）第二名
6. 2023年福州大学青年五四奖章
7. 2020年国际集成电路计算机辅助设计竞赛（CAD Contest@ICCAD）第二名
8. 2019年“互联网+”中国大学生创新创业大赛金奖，创意组全国第一名
主要论著：
1. Chuandong Chen, Disi Lin, Qinghai Liu, Huan He, Zhifeng Lin*, Genggeng Liu, Jianli Chen, Yao-Wen Chang, A Matching Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Early Access, 2025.
2. Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, and Yao-Wen Chang, Electrostatics-Based Analytical Global Placement for Timing Optimization, IEEE/ACM Design, Automation and Test in Europe (DATE), Valencia, Mar. 25-27, 2024.
3. Xingyu Tong, Guohao Chen, Min Wei, Zhijie Cai, Peng Zou, Zhifeng Lin*, and Jianli Chen, Layout-level Hardware Trojan Prevention in the Context of Physical Design, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27–31, 2024.
4. Jihai Meng, Shaohong Weng, Zhijie Cai, Yilu Chen, Zhifeng Lin*, and Jianli Chen, Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion, IEEE/ACM Design Automation Conference (DAC), San Francisco, Jun. 23-27, 2024.
5. Yilu Chen, Zhijie Cai, Min Wei, Zhifeng Lin*, Jianli Chen, Global and Local Attention-Based Inception U-Net for Static IR Drop Prediction, IEEE International Conference on Computer Design (ICCD), Milan, Nov. 18-20, 2024.
6. Yilu Chen, Zhifeng Lin*, Xiaojian Liang, Zhijie Cai, Xiqiong Bai, and Jianli Chen, Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 71(9), pp. 4201-4205, 2024
7. Xingyu Tong, Zhijie Cai, Peng Zou, Min Wei, Yuan Wen, Zhifeng Lin*, and Jianli Chen, O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, Jan. 22-25, 2024.
8. Min Wei, Xingyu Tong, Zhijie Cai, Peng Zou, Zhifeng Lin*, and Jianli Chen, An Analytical Placement Algorithm with Routing topology Optimization, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Incheon, Jan. 22-25, 2024.
9. Yuan Wen, Benchao Zhu, Zhifeng Lin*, and Jianli Chen, Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Jan. 22-25, 2024.
10. Peng Zou, Guohao Chen, Zhifeng Lin, Jun Yu and Jianli Chen, Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 09-13, 2023.
11. Peng Zou, Zhijie Cai, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen, Incremental 3D Global Routing Considering Cell Movement and Complex Routing Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 42(6):2016-2029, 2023.
12. Zhifeng Lin, Yanyue Xie, Peng Zou, Sifei Wang, Jun Yu and Jianli Chen, An Incremental Placement Flow for Advanced FPGAs with Timing Awareness, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 40(9):3092-3103, 2022.
13. Jianli Chen, Zhifeng Lin, Yanyue Xie, Wenxin Zhu and Yao-Wen Chang, Mixed-cell-height Placement with Complex Minimum-Implant-Area Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(11): 4639-4652, 2022.
14. Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu and Yao-Wen Chang, Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints, IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, Feb. 01-05, 2021.
15. Peng Zou, Zhifeng Lin, Chenyue Ma, Jun Yu and Jianli Chen, Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement, ACM/IEEE Design Automation Conference (DAC), San Francisco, Dec. 5-9, 2021.
16. Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu and Jianli Chen, Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 19-23, 2020.
17. Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, and Sy-Yen Kuo, Clock-Aware Placement for Large-Scale Heterogeneous FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(12):5042-5055, 2020.
18. Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, and Yao-Wen Chang, Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification, ACM/IEEE Design Automation Conference (DAC), San Francisco, July 19-23, 2020.
